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RFT3055LE
Data Sheet August 1999 File Number
4537.3
2.0A, 60V, 0.150 Ohm, N-Channel, Logic Level, ESD Rated, Power MOSFET
This product is an N-Channel power MOSFET manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. It was designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49158.
Features
* 2.0A, 60V * rDS(ON) = 0.150 * 2kV ESD Protected * Temperature Compensating PSPICE(R) Model * Thermal Impedance SPICE Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RFT3055LE PACKAGE SOT-223 3055L BRAND
Symbol
D
NOTE: RFT3055LE is available only in tape and reel.
G
S
Packaging
SOT-223
DRAIN (FLANGE)
SOURCE DRAIN GATE
8-143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFT3055LE
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified RFT3055LE 60 60 10 2.0 Figure 5 Figures 6, 16, 17 1.1 9.09 -55 to 150 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W mW/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJA Pad Area = 0.171 in2 (see note 2) Pad Area = 0.068 in2 Pad Area = 0.026 in2 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 30V, ID 2.0A, RL = 15 Ig(REF) = 1.0mA (Figure 15) TEST CONDITIONS ID = 250A, VGS = 0V (Figure 11) VGS = VDS, ID = 250A (Figure 10) VDS = 60V, VGS = 0V VDS = 60V, VGS = 0V, TA = 150oC VGS = 10V ID = 2.0A, VGS = 5V (Figure 9) VDD = 30V, ID 2.0A, RL = 15, VGS = 5V, RGS = 5 (Figure 12) MIN 60 1 TYP 0.110 10 70 30 25 28 15 1.0 850 170 100 MAX 2 1 50 10 0.150 120 85 35 18 1.2 110 128 147 UNITS V V A A A ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W oC/W
Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time NOTE: 2. 110 oC/W measured using FR-4 board with 0.171in2 footprint for 1000 seconds. SYMBOL VSD trr TEST CONDITIONS ISD = 2.0A ISD = 2.0A, dISD/dt = 100A/s MIN TYP MAX 1.5 100 UNITS V ns
8-144
RFT3055LE Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) ID, DRAIN CURRENT (A)
Unless otherwise specified
2.5 RJA = 110oC/W 2.0
1.5
1.0
0.5
0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
2 1 ZJA, NORMALIZED THERMAL IMPEDANCE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM
RJA = 110oC/W
0.1
SINGLE PULSE 0.01 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s)
t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 102 103
t1
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
TJ = MAX RATED TA = 25oC IDM, PEAK CURRENT (A)
30
TA = 25oC
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125 RJA = 110oC/W
ID, DRAIN CURRENT (A)
10 100s 1ms 1 10ms 100ms 0.1 RJA = 110oC/W OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
10
VGS = 5V
DC 100 200
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1 10-3 10-2 10-1 100 101 102 103
0.01 0.1
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
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RFT3055LE Typical Performance Curves
20 IAS, AVALANCHE CURRENT (A) 10
Unless otherwise specified (Continued)
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25oC ID, DRAIN CURRENT (A)
20 VGS = 10V 16
VGS = 5V VGS = 4.5V
12
VGS = 4V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC VGS = 3V
1
STARTING TJ = 150oC
8
4
0.1 0.01
0.1 1 10 tAV, TIME IN AVALANCHE (ms)
100
0 0 1 2 3 4 5 VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
20 150oC -55oC 12 25oC NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
2.0 1.75 1.5 1.25 1.0 0.75
ID, DRAIN CURRENT (A)
16
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 2A
8
4
0 0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V)
0.5 -80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.15 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
1.2 VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.1
ID = 250A 1.1
1.0
1.05
0.9
1.0
0.8
0.95
0.7 -80
-40
0
40
80
120
160
0.9 -80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
8-146
RFT3055LE Typical Performance Curves
200 rDS(ON), ON-STATE RESISTANCE (m) VDD = 30V, ID = 2A, RL = 15 tR SWITCHING TIME (ns) 150
Unless otherwise specified (Continued)
250 ID = 2A ID = 0.5A 200
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
100 tF 50 tD(OFF)
150
100
tD(ON) 0 0 30 20 40 10 RGS, GATE TO SOURCE RESISTANCE () 50
50 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10
FIGURE 12. SWITCHING TIME vs GATE RESISTANCE
FIGURE 13. SOURCE TO DRAIN ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
10 VGS , GATE TO SOURCE VOLTAGE (V) WAVEFORMS IN DESCENDING ORDER: ID = 2A ID = 0.5A VDD = 15V
1200 CISS C, CAPACITANCE (pF) 900 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD COSS 300 CRSS 0 0 5 10 15 20 25 30 VDS , DRAIN TO SOURCE VOLTAGE (V)
8
6
600
4
2
0 0 6 12 18 Qg, GATE CHARGE (nC) 24 30
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 15. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
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RFT3055LE Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Ig(REF) 0 VGS = 5V
DUT Ig(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORM
tON td(ON) RL VDS VGS VGS
+
tOFF td(OFF) tr tf 90%
VDS
90%
0V RGS DUT
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 20. SWITCHING TIME TEST CIRCUIT
FIGURE 21. RESISTIVE SWITCHING WAVEFORMS
8-148
RFT3055LE Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJ(MAX), and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PD(MAX), in an application. Therefore the application's ambient temperature, TA (oC), and thermal impedance RJA (oC/W) must be reviewed to ensure that TJ(MAX) is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T J ( MAX ) - T A ) P D ( MAX ) = -------------------------------------------R JA
200 RJA = 75.9 - 19.3 * ln(AREA) 147oC/W - 0.026in2 RJA (oC/W) 150 128oC/W - 0.068in2 110oC/W - 0.171in2 100
(EQ. 1)
50 0.01 0.1 AREA, TOP COPPER AREA (in2) 1.0
In using surface mount devices such as the SOT-223 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of the PD(MAX) is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Intersil provides thermal information to assist the designer's preliminary application evaluation. Figure 22 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow.This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve.
FIGURE 22. THERMAL RESISTANCE vs MOUNTING PAD AREA
Displayed on the curve are the three RJA values listed in the Electrical Specifications table. The three points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PD(MAX). Thermal resistances corresponding to other component side copper areas can be obtained from Figure 22 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.
R JA = 75.9 - 19.3 x ln ( Area ) (EQ. 2)
8-149
RFT3055LE PSPICE Electrical Model
.SUBCKT RFT3055LE 2 1 3 ;
CA 12 8 1.68e-9 CB 15 14 1.78e-9 CIN 6 8 7.69e-10
LDRAIN
REV May 98
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 64.28 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.6e-9 LSOURCE 3 7 4.6e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 24e-3 RGATE 9 20 9.84 RLDRAIN 2 5 10 RLGATE 1 9 46 RLSOURCE 3 7 46 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 49e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1 LGATE
DPLCAP 10
5 RLDRAIN
DRAIN 2
RSLC2
RSLC1 51 + 5 ESLC 51 50 RDRAIN 16
DBREAK 11 + EBREAK 17 18 MWEAK DBODY
ESG
6 8 +
EVTEMP RGATE + 18 9 20 22 DESD1 91 DESD2
EVTHRES + 19 8 6
21 MMED MSTRO
RLGATE
CIN
LSOURCE 8 RSOURCE 7 SOURCE 3 RLSOURCE
S1A 12 13 8 S1B 13 CA EGS
S2A 15 14 13 S2B CB + 6 8 EDS 5 8 8 14
RBREAK 17 18 RVTEMP IT 19 VBAT + 22 RVTHRES
+
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*45),4))} .MODEL DBODYMOD D (IS = 3.61e-13 RS = 1.78e-2 TRS1 = 1.7e-2 TRS2 = -4.69e-6 CJO = 3.88e-10 TT = 3.6e-8) .MODEL DBREAKMOD D (RS = 4.73e-1 TRS1 = -2.19e-3 TRS2 = 4.7e-5) .MODEL DESD1MOD D (BV = 12.5 NBV = 17.5 IBV = 2.5e-4 RS = 22) .MODEL DESD2MOD D (BV = 12.86 NBV = 22 IBV = 2.5e-4 RS = 0) .MODEL DPLCAPMOD D (CJO = 4.803e-10 IS = 1e-30 N = 10) .MODEL MMEDMOD NMOS (VTO = 1.78 KP = 1.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 9.84) .MODEL MSTROMOD NMOS (VTO = 2.08 KP = 10.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.55 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 98.4 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.06e-3 TC2 = -6.22e-7) .MODEL RDRAINMOD RES (TC1 = 4.5e-3 TC2 = 6e-5) .MODEL RSLCMOD RES (TC1 = 0 TC2 = 0) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC = 0 TC2 = -4e-6) .MODEL RVTEMPMOD RES (TC1 = -1.9e-3 TC2 = 1.3e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4.4 VOFF= -2.4) VON = -2.4 VOFF= -4.4) VON = -2.0 VOFF= 1.15) VON = 1.15 VOFF= -2.0)
.ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8-150
RFT3055LE SPICE Thermal Model
REV May 98 RFT3055LE Copper Area = 0.077in2 CTHERM1 9 8 7.5e-5 CTHERM2 8 7 3.5e-4 CTHERM3 7 6 1.2e-3 CTHERM4 6 5 1.5e-2 CTHERM5 5 4 6.0e-2 CTHERM6 4 3 3.0e-1 CTHERM7 3 2 1.6 CTHERM8 2 1 6 RTHERM1 9 8 8.2e-2 RTHERM2 8 7 2.7e-1 RTHERM3 7 6 1.9 RTHERM4 6 5 3.1 RTHERM5 5 4 12 RTHERM6 4 3 38 RTHERM7 3 2 32 RTHERM8 2 1 22
9 JUNCTION
RTHERM1
CTHERM1
8
RTHERM2
CTHERM2
7
RTHERM3
CTHERM3
6
RTHERM4
CTHERM4
5
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
RTHERM7
CTHERM7
2
RTHERM8
CTHERM8
1
AMBIENT
8-151
RFT3055LE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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